Analog phase locked loop holdover

摘要

A phase locked loop (PLL) circuit is provided having: (1) a phase detector coupled to a reference clock signal and a feedback signal for generating positive and negative phase detection signals corresponding to the phase difference between the reference clock signal and the feedback signal; (2) an integrator coupled to the positive and negative phase detection signals for generating an output voltage proportional to the pulse width of either the positive or negative phase detection signals, the integrator including an operational amplifier having positive and negative inputs; (3) a voltage controlled oscillator coupled to the output voltage of the integrator for generating a local oscillator signal with an oscillation frequency proportional to the output voltage of the integrator; (4) a feedback circuit coupled to the local oscillator signal for generating the feedback signal; and (5) an analog holdover circuit for generating an input to the integrator when the phase detector stops receiving the reference clock signal.