| 摘要 |
PURPOSE: An apparatus for No.7 protocol processing in a switching system is provided to minimize wrong operations by preventing data loss due to the loading and unloading of other boards and to decrease an error generation probability by reducing buffering frequency in processing the data between level 2 and level 3. CONSTITUTION: An SSPHA board(300) can process four No.7 signaling links. The No.7 data received through an SHW are inputted to an MK5027(301), a No.7 level 2 processing dedicated unit in the SSPHA board(300). The MK5027(301) filters level 2 associated data among the received No.7 data and writes level 3 data in a DPRAM(302), a buffer. At this moment, an MPC860(303) continuously monitoring the DPRAM(302), if the No.7 data are written from the MK5027(301), brings the data to an internal DRAM and processes some functions of level 3. Then the MPC860(303) completes a final No.7 data processing by sending the other level data to an ASP through an IS bus using an HDLC controller.
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