| 摘要 |
PURPOSE: A 2M clock multiplier for a high speed digital communication system is provided, which uses only digital devices in order to be embodied easily on a chip. CONSTITUTION: A frequency multiplier includes the first or the Mth delay blocks(100,200,300,...,400) each controlled by a control signal of L bits, an XOR gate(500) performing an XOR operation of an output of the first delay block(100) and a reference clock(CKref) of a constant period(T), and an OR gate(600) making a clock(CK2m) by multiplying the reference clock by 2M times by performing an OR operation of the outputs of the second or the Mth delay block(200,300,...,400). The first delay block generates a delay clock(CKdly) by delaying the reference clock by T/4M under the control of Lcom bit of the control signal. The XOR gate generates a synchronous clock(CKbas) by performing an XOR operation of the delay clock and the reference clock. The OR gate outputs a 2M-multiplied clock(CK2m) by an OR operation of (M-1) T/2M-delayed clock generated from the second or the Mth delay block.
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