发明名称 AUTOMATIC ARRANGING AND WIRING METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To solve such a problem that when two kinds of LSI layouts differing in wiring grid interval are combined, a nonconnection part is formed between a terminal and a wire to bring about the need to manually arrange a wire at the nonconnection part and there is the possibility of a long time needed for the layouts, large time loss, and an increase in chip area when the layouts are adjusted to one wiring grid interval. SOLUTION: Terminals 16 and 17 having x-directional length (x2+(L/2)) and y-directional length (y2+(L/2)) are arranged. Wires 11 and 12 of a necessary microblock are arranged along a wiring grid 10 and then wires 14 and 15 are automatically wired along a wiring grid 13 on a chip. When the terminals 16 and 17 are viewed on the wiring grid 13 of a higher chip, more than one wiring grid is crossed in the x direction and y direction without fail, so the wires 14 and 15 on the chip are connected to the wires 11 and 12 of the microblock through the terminals 16 and 17 without fail.
申请公布号 JP2001306641(A) 申请公布日期 2001.11.02
申请号 JP20000127322 申请日期 2000.04.27
申请人 VICTOR CO OF JAPAN LTD 发明人 SHIMIZU TAKESHI
分类号 G06F17/50;H01L21/82;(IPC1-7):G06F17/50 主分类号 G06F17/50
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