发明名称 MULTIPLE BUS CONTROLLER
摘要 PROBLEM TO BE SOLVED: To shorten the time of arbitration and to improve the data transfer efficiency of a multiple bus. SOLUTION: A request device 34 outputs the priority data one by one in the order of higher rank bits as arbitration signals in a propriety decision processing mode and then outputs the identification numbers as arbitration signals in the form of original multivalued data signals in an allocation processing mode. An adder device 36 adds together the arbitration signals which are outputted from all devices 34. Thus, the number of conflictive modules which transmitted communication request signals in the same timing is known in the propriety decision processing mode and the identification numbers of all modules whose communication are permitted are known in the allocation processing mode. On the basis of the addition result of arbitration signals, the number of conflictive modules is compared with the number of idle channels in the propriety decision processing mode. Thereby the propriety is decided at a time for permission of communication about plural modules 12 and the communication is permitted for the modules 12 in the order of higher priorities. In the allocation processing mode, the identification numbers of modules 12 whose communication are permitted are extracted and the idle transmission channels are allocated to these modules 12.
申请公布号 JP2001306494(A) 申请公布日期 2001.11.02
申请号 JP20000116522 申请日期 2000.04.18
申请人 FUJI XEROX CO LTD 发明人 KAMIMURA TAKESHI;KOSEKI SHINOBU;MIURA MASAAKI
分类号 G06F3/00;G06F13/36;G06F13/362;H04L12/40;H04L29/04;H04L29/06;(IPC1-7):G06F13/36 主分类号 G06F3/00
代理机构 代理人
主权项
地址