摘要 |
<p>PROBLEM TO BE SOLVED: To improve sense margin and to increase operation speed. SOLUTION: Load capacitors Cr1,..., Crm having respectively almost same load capacitance as banks 0A,..., mA selected by an address signal are respectively coupled to a reference bit line BBr using corresponding transistors Lt0,..., Ltm, even when the number of banks is in creased or decreased, capacitance can be increased or decreased by switching the number of load capacitors added to the reference line BBr by an inputted address. Therefore, load capacitance of a bit line from a memory cell MC to a sence amplifier SA and load capacitance of a reference line BBR can be adjusted so as to be equal, sense margin is improved, and an access time (sense speed) can be shortened.</p> |