| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a demultiplexer which can cope with a plurality of multiplexing systems, and further reduce circuit scale and decrease cost. SOLUTION: A control section 113 generates a control signal controlling each section on the basis of a micro code sequentially read from an instruction memory 111. A shift register 102 stores received packets. A register group 103 captures a header of the packets as required and an arithmetic section 104 analyzes them. An output destination decision section 105 decides an output destination by a packet ID in the header. A demultiplexer section 106 demultiplexes an optional packet from an output of the sift register 102 depending on the arithmetic result of the arithmetic section 104 and a decision result of an output destination and outputs the demultiplexed packet to a prescribed output destination. The shift register 102 detects timing information from the received packet and supplies it to a clock control section 114 to control a system clock. By altering the micro code read from the instruction memory 111, the demultiplexer is allowed to cope with a plurality of multiplex systems, the circuit scale can be reduced and the cost-down attained.</p> |
