发明名称 METHOD AND DEVICE FOR AUTOMATIC ARRANGEMENT AND WIRING AND SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To solve the problem that a wire becomes easier to break because of high wire resistance and also becomes deficient in reliability and the rearrangement of the wire requires labor and requires a longer design time when the wire having a wiring filling factor above an upper-limit value is made thin. SOLUTION: The wiring filling factor is checked by scanning a specific measurement area on a layout pattern of wiring. When the wire filling factor exceeds the upper-limit value, wiring intervals are automatically widened so that the wire filling factor becomes less than the upper-limit value, a wiring inhibition area is inserted between wires, wiring is divided into and replaced by plural wirings having marrow width, or part of a wire is formed in a layer through a contact hole to obtain a layout pattern whose wire filing factor is less than the upper-limit value.
申请公布号 JP2001306640(A) 申请公布日期 2001.11.02
申请号 JP20000115580 申请日期 2000.04.17
申请人 MITSUBISHI ELECTRIC CORP 发明人 TANAKA GENICHI
分类号 G06F17/50;H01L21/82;(IPC1-7):G06F17/50 主分类号 G06F17/50
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