发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT, DESIGNING METHOD AND METHOD OF MANUFACTURE
摘要 PROBLEM TO BE SOLVED: To resolve problems of the conventional test method of a semiconductor integrated circuit, i.e., a long test time, a high test cost, and yield reduction by the generation of failures due to the test circuit itself. SOLUTION: Memory elements (MC1-MC4) are comprised, a plurality of variable logic cells (LCL) that can output any logical output corresponding to an input by means of the memory information of the memory elements are closely laid on the area except the circuit blocks (CPU, ROM) on a semiconductor chip, and this integrated circuit is constituted so as to test the circuit block in the chip by using this variable logic cell.
申请公布号 JP2001308271(A) 申请公布日期 2001.11.02
申请号 JP20000117001 申请日期 2000.04.18
申请人 HITACHI LTD 发明人 SATO MASAYUKI;UCHIYAMA KUNIO
分类号 H01L21/822;G11C7/18;G11C16/04;G11C29/08;G11C29/44;H01L21/82;H01L27/04;(IPC1-7):H01L27/04 主分类号 H01L21/822
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