| 摘要 |
Disclosed is a clock period sensing circuit in which it is possible to broaden the operating range of phase adjustment and frequency multiplier circuits, etc., by performing coarse period adjustment in advance. A plurality of delay sensing circuits having slightly overlapping operating ranges and different centers of operation are connected in parallel with respect to a an input clock signal, which is passed through the delay sensing circuits. The period of the clock is sensed coarsely in short periods using a signal which identifies delay sensing circuits through which the clock signal has passed and delay sensing circuits through which the clock signal has not passed.
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