| 摘要 |
<p>The present invention discloses a delay clock pulse-width adjusting circuit for intermediate frequency or high frequency. The circuit includes delay comparer and source, and it further includes: For the delay comparer, it compares one of its inputs sine wave signal and another input voltage then outputs clock signal with specific duty ratio; and a convert circuit which converts the clock signal duty ratio to direct current level, the input end of the circuit receives said clock signal from the output end of the delay comparer and converts the signal to said direct current level, and the output end of said convert circuit sends said direct current level to said another input end of said delay comparer. With the adjusting circuit, it makes the duty ratio of clock signal changed not abrupt, it also reduce the pressure of digital signal process, and it satisfied with the high information quantity, low error code ratio, high stability of duty ratio of clock signal.</p> |
