| 摘要 |
A fractional-N frequency synthesiser having an increased range of fractional control values outside the usual range {0,1}. The synthesiser is based on a PLL (10) having a frequency divider (25) controlled by an improved modulator system (20, 27). Noise and fractional spurs in the output of the PLL (10) are reduced. The modulator includes a multi-level quantizer (60, 150) with additional logic operations in output (62) and feedback (63, 153) stages. A cascade of modulators (50, 110) may be used. A dither signal (d) may be added as required within one or more of the modulators.
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