| 摘要 |
A semiconductor memory device comprising first and second gate electrode layers in a first conductive layer, first and second drain-drain connecting layers in a second conductive layer, and first and second drain-gate connecting layers in a third conductive layer. The first and second drain-gate connecting layers are located higher than the first and second gate electrode layers. Therefore, a source contact layer can be located in the region between gate electrode layers while preventing a contact with the second drain-gate connecting layer.
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