发明名称 |
Digital camera |
摘要 |
A digital camera includes a signal processing circuit. The signal processing circuit makes signal processing on the camera data read from a camera data area of an SDRAM to produce YUV data for record. A thin-out circuit makes a thin-out processing on the recording YUV data to produce YUV data for display. The display YUV data and the recording YUV data thus produced are written respectively to a display data area and a recording data area of the SDRAM and thereafter processed for display on a display and record to a flash memory. The access speed to SDRAM is 48 MHz and the processing speed of the signal processing circuit and thin-out circuit is 12 MHz. Consequently, the YUV data for display and YUV data for record is written concurrently with reading out of the camera data.
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申请公布号 |
US2001036359(A1) |
申请公布日期 |
2001.11.01 |
申请号 |
US20010784308 |
申请日期 |
2001.02.16 |
申请人 |
NISHIKAWA MASAHIKO;KANDA TAKEHIKO |
发明人 |
NISHIKAWA MASAHIKO;KANDA TAKEHIKO |
分类号 |
H04N5/232;H04N5/77;H04N5/907;H04N9/804;(IPC1-7):H04N5/76;H04N5/225 |
主分类号 |
H04N5/232 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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