| 摘要 |
PURPOSE: A semiconductor memory device is provided to prevent a data failure by making a precharge time of a write operation fast during a read and write operation. CONSTITUTION: The first equalizer transistor(31) makes levels of a pair of main input/output signal(MIOT/B) equal by receiving an external equalizer main input/output signal(EQMIOT), and a VDL precharge circuit(32) precharges the MIOT/B. A switching transistor(33) inputs/output the MIOT/B signal to/from a pair of local input/output signal(LIOT/B). The second equalizer transistor(34) makes levels of a pair of local input/output signals equal by receiving the equalizer main input/output signal(EQMIOT) and is used for a next burst operation. An inverter(35) outputs an inverted signal(BLEQB) by receiving an external bit line precharge signal(ELEQ). The third equalizer transistor(36) makes levels of the LIOT/B signal equal by receiving an output signal(BLEQB) of the inverter, and a VBLR precharge circuit(37) precharges the LIOT/B as a bit line precharge voltage signal.
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