| 摘要 |
<p>An n-channel MISFET (Qn), a p-channel MISFET (Qp) and first to third wiring layers (11 to 13) are formed on the primary side of a silicon substrate (1). Fourth to seventh wiring layers (14 to 17) are formed on the primary side of a glass substrate (30). With the primary sides of the silicon substrate (1) and the glass substrate (30) opposed to each other, micro bumps (20A) on the silicon substrate (1) and micro bumps (20B) on the glass substrate (30) are electrically connected to complete a CMOS logic LSI.</p> |
