| 摘要 |
<p>A technique for precisely calculating the delay time of an electronic circuit device where the signal reach times of a wiring of concern and the wirings adjacent to the wiring of concern dynamically vary depending on the input signal pattern by analyzing the delay time deterioration due to the crosstalk between the wirings. By using information about the delay time deterioration retrievable by using relative signal reach times between the wiring of concern and the adjacent wirings, the delay time deterioration occurring in each pair of a wiring of concern and the adjacent wiring is calculated for each signal reach time of the wiring of concern, and the delay time deteriorations are summed to calculate the total delay time deterioration when two or more adjacent wirings are present. The designing of a high-speed large-scale electronic circuit device can be facilitated, and extra margin for delay time can be excluded, thereby resulting in that an electronic circuit device can be efficiently designed and manufactured.</p> |
