Endian conversion of plural-byte units without delay

摘要

An endian conversion apparatus includes a first switch (1a). The first switch (1a) inputs an input byte data (DA1), a data size signal (DS), an endian switch signal (ES) and a byte enable data (BE1) to output an output byte data (DA2) on which a second endian representation is performed. The input byte data (DA1) includes a plurality of byte data on which a first endian representation is performed. The data size signal (DS) indicates the number of bytes to be recognized as a unit data. The endian switch signal (ES) indicates an execution of an endian conversion. The byte enable data (BE1) indicates a byte position to be recognized as the unit data. The first endian representation is performed on the byte enable data (BE1). The first switch (1a) outputs the output byte data (DA2) having the number of bytes indicated by the data size signal (DS) when the endian switch signal (ES) indicates the execution. An array of the byte position indicated by the byte enable data (BE1) is maintained in the output byte data (DA2). <IMAGE>