APPARATUS FOR CORRECTING ERROR OF HIGH-SPEED DATA

摘要

PURPOSE: An apparatus for correcting an error of high-speed data is provided to form a low-priced error correction device by using a system buffer without a delay buffer. CONSTITUTION: A system buffer(10) receives and stores data including parity bits in block units and outputs the received data in symbol units. A calculation portion(12) performs a syndrome calculation for symbols of the system buffer(10) and outputs a location and a value of an error. A latch(20) latches the input data. An adder(26) receives an output and an error value of the latch(20) and corrects the error. The first buffer(24) stores the location of the error. The second buffer(22) stores the value of the error. The first counter portion(30) counts inner codes of the symbols. The second counter(40) counts outer codes of the symbols. A multitude of multiplexers(28,36,46,48) multiplex the outputs of the first and the second counter portions(32,42). An address generation portion(50) generates an address of correcting data by using a counter value and an error location value of the multiplexers(28,36,46,48).