| 摘要 |
According to the invention, a frequency demultiplication circuit serves to generate wander or wander sequences having frequencies of less than 10 Hz and, in particular, less than 1 Hz. Said frequency demultiplication circuit receives, on the input side, pulse signals of a relatively high frequency and has two counter arrays (C11, C12; C21, C22) and a phase comparator circuit (COMg) that is connected to the outputs of said counter arrays. The counting cycle of one counter array (C22) is modified with regard to the counting cycle of the other counter array (C12) within a period of the respective wander to be generated or of the respective wander sequence to be generated according to a desired progression of the wander or of the wander sequence.
|
