| 摘要 |
A method for verifying all intermediate results of a set of architected registers at the end of an instruction stream, even if the final values do not depend on the values of all intermediate results, using a single MISR (Multiple Input Shift Register) to generate a signature of all updates to multiple architected registers. Single instructions update multiple registers across multiple machine cycles, and an accumulation register allows order independence of partial results. A register update consists of the data to be written, an address identifying which register is to be updated, and controls to identify if this is the last register update that will be done by the current instruction. For each cycle, logic evaluates the update controls to select what will be gated into the accumulation register and also sets MISR control latches to tell how to update the MISR the next cycle. The latched MISR controls select whether the MISR will clear, hold, or evaluate. The expected final MISR value (signature) is compared to the actual final MISR value (signature). A mismatch indicates a functional error during execution of the instruction stream.
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