发明名称 Process for forming high voltage junction termination extension oxide
摘要 A process for forming a junction termination extension (JTE) oxide having reduced total oxide charge and SiO2-Si interface trap density parameters uses precursor densified thin oxide layers to improve the quality of subsequently formed thicker oxide layers, and multiple anneals to remove implant damage and set geometry parameters. After formation of a first dual oxide layer, and a post-oxidation anneal, the oxide is patterned and JTE regions are implanted. Implant-based near surface crystalline damage is annealed out in a non-oxidizing ambient, and JTE dopants are partially driven into adjoining material of the substrate. A thin dense bulk precursor oxide layer is grown on the exposed JTE dopant-implanted surface portions of the substrate, followed by forming the bulk of the JTE oxide in a steam or wet oxygen atmosphere. The substrate is then annealed in a non-oxidizing ambient, to cause a further drive-in of the JTE dopants. The associated reduction in Qox and Dit improves high voltage edge stability.
申请公布号 US6309952(B1) 申请公布日期 2001.10.30
申请号 US19980167177 申请日期 1998.10.06
申请人 FAIRCHILD SEMICONDUCTOR CORPORATION 发明人 RIDLEY RODNEY S.;TROST JASON R.;WEBB RAYMOND J.
分类号 H01L21/033;H01L21/225;H01L21/266;H01L21/316;H01L29/06;(IPC1-7):H01L21/425 主分类号 H01L21/033
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