| 摘要 |
A PLL circuit comprises a storage/control circuit for storing, in an associated manner, a plurality of PLL output frequencies to be designated, lock ranges including the PLL output frequencies in their central regions respectively, and information on the number of stages of delay circuits. The number of stages of the delay circuits having a lock range including a designated PLL output frequency in its central region is selected and controlled by the storage/control circuit. A frequency divider selects and controls a frequency division ratio for obtaining a PLL output frequency on the basis of a frequency of a reference signal.
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