| 摘要 |
An intermediate-frequency signal is fed to a demodulated-signal processing circuit through a variable gain circuit, an active filter, and a limiter. An RSSI output signal responsive to a received signal level is obtained through a low-pass filter by detecting the output of each stage of the limiter at a detector and by summing the output of the detector at an adder. The linearity of the RSSI output signal responsive to the received signal level is improved by feeding, via a coefficient multiplier to the adder, the control signal of a level detector which detects the control signal of the variable gain circuit, which limits the signal input to the active filter.
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