Integrated circuit device having a burn-in mode for which entry into and exit from can be controlled

摘要

An integrated circuit structure and method provides a burn-in stress test mode that facilitates stress testing of an integrated circuit device in a burn-in oven. The integrated circuit structure and method is capable of disabling a time-out feature of an IC memory device during a stress test mode of the device in order to facilitate stress testing of the device in a burn-in oven. The integrated circuit structure provides for entry into the burn-in stress test mode when a supply voltage supplied to the integrated circuit device exceeds a predetermined voltage level and/or the temperature of the integrated circuit device exceeds a predetermined temperature level.