| 摘要 |
A test circuit enables a memory tester to test for defective memory cells in a memory portion of an Embedded DRAM or other memory device having a relatively wide internal data path. The Embedded DRAM includes a memory having an array of memory cells, the memory being coupled to a logic circuit. The test circuit includes at least one external terminal and a plurality of data masking circuits. Each data masking circuit is coupled to a respective one of the arrays and transfers data signals to and from addressed memory cells in the array. The data signals are selectively masked responsive to a data masking signal. A plurality of data compression circuits each is coupled to a respective data masking circuit to receive a respective data signal. Each data compression circuit compares each of the data signals applied on its respective inputs to an expected value and generates an active error signal on a respective external terminal responsive to any of the applied data signals not having the expected value. When the test mode signal goes active, a test control circuit applies addressed data to the data masking circuits. The control circuit initially disables the data masking signals so the addressed data is not masked and controls the data compression circuits to generate the respective error signals responsive to the applied data. When at least one the error signals goes active, the test control signal goes active causing the test control circuit to control the data masking signals to sequentially mask each data signal applied to the data masking circuit that generated the active error signal to enable an external tester to detect a defective memory cell from the error signals.
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