发明名称 RECEPTION DELAY ADDING CIRCUIT FOR ULTRASONOGRAPH
摘要 PROBLEM TO BE SOLVED: To provide a reception delay adding circuit in which deflection of a received signal is not generated due to current saturation, or the like, on a delay line. SOLUTION: An input circuit 62 connected to a tap of a delay line 60 is constituted by a pair of transistors with a complementary constitution and being grounded to a base. In this input circuit, the bias current in a transistor TRP0 is absorbed in a transistor TRN0 as a bias current in the TRN0. In this way, the bias current does not flow into the tap connected to the connection point between the TRP0 and the TRN0. Also, input circuits 64 and 66 of adjacent taps are constituted so as to have complementary constitutions. In this way, the bias current flowed into the delay line 60 from the input circuit 64 is absorbed from the delay line 60 as the bias current of the input current 66. By constituting this way, only the signal current is cumulatively added on the delay line 60.
申请公布号 JP2001299760(A) 申请公布日期 2001.10.30
申请号 JP20000120017 申请日期 2000.04.20
申请人 ALOKA CO LTD 发明人 MINAMISHIMA MAMORU;KIMITA YUUJI
分类号 A61B8/14;A61B8/00;(IPC1-7):A61B8/14 主分类号 A61B8/14
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