发明名称 |
Multi-bank semiconductor memory device suitable for integration with logic |
摘要 |
Subbanks are arranged in four regions of a DRAM macro having a rectangular shape, bank control circuits are arranged in a prescribed region between these subbanks, and internal read/write data buses are arranged in a region different from the region where the bank control circuits are arranged. Since there is no crossing of the bank control circuits and the internal read/write data buses, the bank control circuits can be efficiently arranged to reduce the layout area. Accordingly, a semiconductor integrated circuit device including multi-bank memories which operates stably at high speed can be provided without increase of an area occupied by a chip.
|
申请公布号 |
US6310815(B1) |
申请公布日期 |
2001.10.30 |
申请号 |
US19980131346 |
申请日期 |
1998.08.07 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
YAMAGATA TADATO;YAMAZAKI AKIRA;TOMISHIMA SHIGEKI;YUKINARI YOSHIO;HATAKENAKA MAKOTO;MIYANISHI ATSUSHI |
分类号 |
G11C11/409;G11C5/14;G11C8/12;G11C11/401;H01L21/8242;H01L27/108;(IPC1-7):G11C8/00 |
主分类号 |
G11C11/409 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|