发明名称 ARITHMETIC PROCESSING APPARATUS
摘要 PROBLEM TO BE SOLVED: To add an expansion instruction to an existent mechanism by the minimum change of a design. SOLUTION: This processing apparatus is provided with an instruction decoder 10 for decoding an existent instruction and an expansion instruction to the same operation code including an instruction kind decision bit for deciding at least the existent instruction and the expansion instruction, an existent arithmetic unit 12A for carrying out existent arithmetic based on the operation code and outputting an arithmetic completion information signal DN1, an expansion arithmetic unit 12B operating synchronizing with the unit 12A to carry out expansion arithmetic, based on the operation code, a control circuit 11 for judging the kind of an instruction based on the instruction kind decision bit, and a multiplexer 13 for selecting expansion instruction arithmetic result data EB1 when the kind of the instruction is decided to be the expansion instruction and the signal DN1 is inputted.
申请公布号 JP2001296999(A) 申请公布日期 2001.10.26
申请号 JP20000111340 申请日期 2000.04.12
申请人 FUJITSU LTD 发明人 SUGANO FUMITAKE;TAKESHITA KATSUNORI
分类号 G06F9/30;G06F9/318;G06F9/44;(IPC1-7):G06F9/30 主分类号 G06F9/30
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