发明名称 |
FREQUENCY DIVIDER CIRCUIT |
摘要 |
PROBLEM TO BE SOLVED: To solve a problem that there is a limit to power reduction in the conventional frequency divider circuit using a binary counter frequency divider circuit at high frequencies. SOLUTION: A Johnson counter frequency divider circuit and the binary counter frequency divider circuit are combined. The diagram 1 is a circuit block for combining them, and the power in a high frequency driving part can be suppressed.
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申请公布号 |
JP2001298358(A) |
申请公布日期 |
2001.10.26 |
申请号 |
JP20000112792 |
申请日期 |
2000.04.14 |
申请人 |
CITIZEN WATCH CO LTD |
发明人 |
YANO TAKAKAZU;IWAKURA YOSHIKI;OTAKA YUKIO;AIHARA KATSUYOSHI;KOMINE SHINICHI |
分类号 |
H03K21/00;H03K23/00;H03K23/66;(IPC1-7):H03K23/00 |
主分类号 |
H03K21/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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