发明名称 LAYOUT COMPACTION METHOD
摘要 PROBLEM TO BE SOLVED: To improve the degree of integration of a semiconductor integrated circuit device by performing layout compaction considering an optical proximity effect also for a layout pattern included in circuit design data and having irregular arrangement. SOLUTION: A compaction condition is generated in a compaction control step 2, an OPC condition is generated in an OPC condition generation step 8, an input layout pattern is compacted by a layout compaction step 3, and an optical proximity effect is corrected by an optical proximity effect correction step 4. A layout pattern obtained after the correction of the optical proximity effect is stored in a corrected layout pattern storing step 5, circuit operation is confirmed by the layout pattern obtained after compaction and the correction of the optical proximity effect in respective verification steps 6, 10, the layout pattern obtained when there is a trouble in the circuit operation is stored in an error data storing step 7, and a compaction condition considering the optical proximity effect and error data is generated again in the step 2. These steps are repeated.
申请公布号 JP2001297126(A) 申请公布日期 2001.10.26
申请号 JP20000113512 申请日期 2000.04.14
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 MUKAI KIYOSHI
分类号 G03F1/00;G03F1/36;G03F1/70;G06F17/50;H01L21/027;H01L21/82;H01L21/822;H01L27/04 主分类号 G03F1/00
代理机构 代理人
主权项
地址
您可能感兴趣的专利