PROCEDE ET DISPOSITIF DE CODAGE ET DE DECODAGE DE DONNEES

摘要

The device includes a memory (1) storing digital information and being connected to a data processing device (10) via a bus line. The memory can be accessed by a bidirectional circuit (2) with two channels: one for emission and the other for reception. A FIFO buffer memory (3) is inserted along the emission channel. The buffer memory is connected to an error correcting circuit (4) which applies the Viterbo algorithm. The reception channel is connected to a decoding circuit (7) linked to a second FIFO buffer memory (6).