CLOCK GENERATING CIRCUIT, AND SEMICONDUCTOR MEMORY PROVIDED WITH IT

摘要

PROBLEM TO BE SOLVED: To enlarge a frequency range capable of locking as to a clock generating circuit and to reduce its layout area. SOLUTION: This DLL circuit 100 is provided with a delay circuit 110 for generating an output clock signal SIGOUT by delaying an input clock signal SIGIN and a phase comparing circuit 120 for comparing a phase of the output clock signal SIGOUT with that of the input clock signal SIGIN. The delay circuit 110 comprises plural delay units whose delay vary respectively in accordance with a drive potential Vc. The DLL circuit 100 is provided with a delay control circuit 130 controlling activation of a delay unit in accordance with a phase comparison result of the phase comparing circuit 120 and a drive potential control circuit 140 for controlling a drive potential Vc in accordance with the comparison result of the phase comparing circuit 120.