发明名称 INTEGRATED SEMICONDUCTOR DEVICE
摘要 <p>PROBLEM TO BE SOLVED: To provide an integrated semiconductor device that can achive fine finish by planarizing the device, and at the same time can increase alignment accuracy. SOLUTION: An integrated semiconductor device 1 has (n+1) patterns Pa1 to Pa3 (n indicates a natural number) that are arranged in a first direction that becomes a read direction in pattern recognition, and three patterns Pc1 to Pc3 that are formed at a mark proximity region Rc1 and are provided in at least the first direction. In this case, when each pitch in the first direction of the patterns Pa1 to Pa3 is set to d1 and d2, pitch in the first direction of the pattern Pc1 to Pc3 is set to dD, and distance from the pattern Pa1 is set to D, dD is set so that the relations of|(dD-D1)/d1|>=αand|(dD-d2)/d2|>=α(1>α>0) are met in the mark proximity region Rc1 where at least D<=d1+d2 is established.</p>
申请公布号 JP2001297958(A) 申请公布日期 2001.10.26
申请号 JP20000115120 申请日期 2000.04.17
申请人 TOSHIBA CORP 发明人 ARAI FUMITAKA;TAKEUCHI YUJI
分类号 H01L21/027;G03F9/00;H01L23/544;(IPC1-7):H01L21/027 主分类号 H01L21/027
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