发明名称 Design verification method, design verification device for microprocessors, and pipeline simulator generation device
摘要 In the design verification method, the design verification device, and the pipeline simulator generation device for microprocessors, a pipeline simulator (4, S4, S12) and verification programs for a microprocessor as a target in design are automatically generated (7, S9, S10) based on a pipeline specification described in a description language readable and analyzable by a computer, and the pipeline operation of the microprocessor is verified (12, S15, S16) based on the results (S13) of the simulation (11) of the RTL description and the result (6, S14) of the pipeline simulation performed based on the verification programs and the pipeline simulator.
申请公布号 US2001034594(A1) 申请公布日期 2001.10.25
申请号 US20010816480 申请日期 2001.03.26
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 KOHNO KAZUYOSHI;MIZUNO ATSUSHI
分类号 G06F11/26;G06F17/50;(IPC1-7):G06F17/50 主分类号 G06F11/26
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