发明名称 Packet transmission/reception processor
摘要 If a packet processing controller at a consumer node has failed to process a received packet within a predetermined amount of time, a packet processing control timer detects a time-out and informs a CPU of that. In response, the CPU issues packet processing suspend instruction and packet transmit instruction for the controller by way of a register. In accordance with these instructions, the controller suspends the current packet processing and produces header and data for a WRS packet, which is transmitted to a producer node through a bus. In this manner, a packet can be processed without causing a time-out at the producer node.
申请公布号 US2001034799(A1) 申请公布日期 2001.10.25
申请号 US20010838181 申请日期 2001.04.20
申请人 MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. 发明人 ITO HIROTAKA;TABIRA YOSHIHIRO
分类号 H04L29/06;H04L12/64;H04L29/08;(IPC1-7):G06F15/16;H04L12/66 主分类号 H04L29/06
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