| 摘要 |
A PLL circuit comprises means (3) for generating a plurality of reference signals (fR1-fR8) of different phases, a primary divider (30) for dividing the output signal (fVCO) from a voltage-controlled oscillator (29) by a factor N1, a secondary divider (31) for dividing the output (fV') from the primary divider by a factor N2, a separator circuit (32) for separating the output (Q1a, Q2a, Q3a) from the secondary divider into a plurality of feedback signals (fV1-fV8), and a phase comparator (12-19) for comparing the feedback signals with the reference signals to produce error signals (ER1-ER8). Since the PLL circuit performs phase comparison multiple times during one cycle of a reference signal, lock-up time decreases. An output signal is divided by only two dividers, i.e., the primary and secondary, rather than four or more used in the prior art.
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