| 摘要 |
A simultaneous and redundantly threaded, pipelined processor executes the same set of instructions simultaneously as two separate threads to provide fault tolerance. One thread is processed ahead of the other thread so that the instructions in one thread are processed through the processor's pipeline ahead of the corresponding instructions from the other thread. The thread, whose instructions are processed earlier, places its uncached reads in a read queue. Subsequently, the second thread places its uncached reads in the read queue. A compare circuit periodically scans the read queue for matching uncached read instructions. If otherwise matching instructions differ in their target address, then a fault has occurred in the processing and the compare circuits initiates fault recovery. If comparison of the two instructions reveals they are identical, the compare circuit allows only a single uncached read instruction to pass to the system main memory. The data returned from the uncached read is replicated and passed to each thread. In this way, transient faults are detected with a minimum amount of hardware overhead and independent of differences in the actual order of program execution or differences in branch speculation.
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