发明名称 Memory LSI failure analysis apparatus and analysis method thereof
摘要 The present invention provides a device, method and storage medium, stored with software programs, which, when a memory LSI defect analysis apparatus is used as a monitoring device to estimate reductions in yield, can shorten the time needed for full manual interpretation of the obtained results, by automatically interpreting the analyzed results obtained, and calculating the period of distribution patterns and the mix rate of regular patterned defects. First in defect number calculation process 71, the total defect number of bits is found; and in factor selection process 61, the factor f is then selected. Next, in regular patterned decision process 62, the value of expected value function T(f) for the selected f is found, and it is decided whether or not it includes regularly patterned defects; and if it is decided that regularly patterned defects are included (process 63), then in regular patterned defect mix rate function calculation process 73, regular pattern defect mix rate function MR(f) is calculated from number of bits n, factor f, and the value of estimated value function T(f). If it is decided that it does not contain regularly patterned defects (process 65), in regular patterned defect mix rate function calculation process 66, regular patterned defect mix rate function MR(f) is assumed to be zero; and finally, in MR(f) calculation completion confirmation process 67, it is confirmed whether or not MR(f) has been found for every f, and if there are factors for which MR(f) has not been found, then it returns to process 61.
申请公布号 US2001034864(A1) 申请公布日期 2001.10.25
申请号 US20010819860 申请日期 2001.03.28
申请人 NEC CORPORATION 发明人 TANAKA MIKIO;SUGIMOTO MASAAKI
分类号 G01R31/28;G11C29/00;G11C29/44;G11C29/48;G11C29/54;(IPC1-7):G11C29/00 主分类号 G01R31/28
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