发明名称 |
Circuit arrangement for use in controlling bridging between two computer communication buses ensures that data on one bus is available to the other bus for a selectable time |
摘要 |
Device comprises a first circuit (1) that connects first (2) and second (3) communications buses and acts as a bus- master for the first bus. A second circuit (4) is connected to the first communications bus and has a first output (5) connected to the input (6) of the first bus-master circuit (1). In the second circuit a wait signal is generated that enable read or write access to the first bus over a chosen number of clock cycles. An independent claim is made for a method for controlling a connection between two communications buses.
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申请公布号 |
DE10019239(A1) |
申请公布日期 |
2001.10.25 |
申请号 |
DE20001019239 |
申请日期 |
2000.04.18 |
申请人 |
FUJITSU SIEMENS COMPUTERS GMBH |
发明人 |
DEMHARTER, NIKOLAUS;KNOEPFLE, ANDREAS |
分类号 |
G06F13/40;(IPC1-7):G06F13/38 |
主分类号 |
G06F13/40 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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