| 摘要 |
PURPOSE: An input/output sense amplifier circuit of a semiconductor memory device is provided to reduce an access time of the semiconductor memory device which includes a latch circuit having a variable voltage gain. CONSTITUTION: An input/output sense amplifier circuit(20') is connected to data input/output lines(DIOj,DIOjB), and comprises a current sense amplifier(14') and a voltage sense amplifier(16') and a latch circuit(18'). The latch circuit includes two differential amplifiers(DF1,DF2) constituted with two PMOS transistors and three NMOS transistors. Each differential amplifier receives signals(DIF,DIFB) from the voltage sense amplifier and has output terminals to output corresponding output signals(DOUT,DOUTB). The latch circuit further includes two resistors(R1,R2) and one PMOS transistor(MP24). One end of a resistor(R1) is connected to an output terminal(DOUT) of the differential amplifier(DF1), and one end of a resistor(R2) is connected to an output terminal(DOUTB) of the differential amplifier(DF2). A source-drain channel of the PMOS transistor(MP24) is connected between another ends of the resistors and its gate is connected to receive a LAT signal or a latch signal.
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