发明名称 Negative gate erase
摘要 A method and system for performing verify erasure comprises applying an erase pulse that provides a substantially high electric field to each I/O in a sector one at a time. This operation is important for single power supply devices since the beginning of erase band to band currents for the entire array are larger than can be supplied by drain pumps. After the first erase pulse, the erase verify routine can be performed on all the IO's together. In one particular example, a Vdrain voltage is selected to be at a substantially high positive voltage and the value of Vgate voltage is at a substantially high negative voltage where the voltage potential between Vdrain and Vgate is also a substantially high voltage.
申请公布号 US6307784(B1) 申请公布日期 2001.10.23
申请号 US20010795856 申请日期 2001.02.28
申请人 ADVANCED MICRO DEVICES 发明人 HAMILTON DARLENE G.;DERHACOBIAN NARBEH;TANPAIROJ KULACHET;SUNKAVALLI RAVI
分类号 G11C11/56;G11C16/04;G11C16/34;H01L27/115;(IPC1-7):G11C16/00 主分类号 G11C11/56
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