| 摘要 |
PURPOSE: A multi-ported memory is provided to receive synchronous and asynchronous memory requests by using an asynchronous and synchronous protocol, and to process the received synchronous and asynchronous memory requests simultaneously so that it can support concurrent activities over multiple channels, including both synchronous and asynchronous operations. CONSTITUTION: The device comprises a synchronous write data bus(112), a synchronous read data bus(114), a synchronous read address bus(116), a synchronous write address bus(118), a synchronous read command bus(120), a synchronous write command bus(122), a synchronous read acknowledge bus(124), a synchronous write acknowledge bus(126). The synchronous write data bus(112) supplies data(SYNCWRDATA) to an MRASR(Multi-Request Asynchronous/Synchronous RAMs, 110a-n) during a synchronous write to the MRASR(110a-n). The synchronous read data bus(114) receives data(SYNCRDDATA) from the MRASR(110a-n) during a synchronous read from the MRASR(110a-n). The synchronous read address bus(116) supplies to the MRASR(110a-n) an address (SYNCRDADDR) of data stored within the MRASR(110a-n) that is to be synchronously read from the MRASR(110a-n). The synchronous write address bus(118) supplies to the MRASR(110a-n) an address (SYNCWRADDR) of a memory location within the MRASR(110a-n) where data is to be synchronously written to the MRASR(110a-n). The synchronous read command bus(120) supplies a synchronous read command(SYNCRD) to the MRASR(110a-n). The synchronous write command bus(122) supplies a synchronous write command(SYNCWR) to an MRASR(110a-n). The synchronous read acknowledge bus(124) receives an acknowledge signal(SYNCRDACK) from the MRASR(110a-n) that a synchronous read command submitted to the MRASR(110a-n) has been performed by the MRASR(110a-n). The synchronous write acknowledge bus(126) receives an acknowledge signal(SYNCWRACK) from the MRASR(110a-n) that a synchronous write command submitted to the MRASR(110a-n) has been performed by the MRASR(110a-n).
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