发明名称 Pipeline processing apparatus for reducing delays in the performance of processing operations
摘要 A decoder decodes a branch instruction. An operating section executes logical, arithmetic, and shift operations. A register file store operation result of the operating section. A program counter counting the address of the present programs. A direct-setting bus is provided to allowing the decoder to directly set an immediate value to the program counter without passing through an output bus of the operating section. And, a switch selectively connects the direct-setting bus or the output bus to the program counter.
申请公布号 US6308263(B1) 申请公布日期 2001.10.23
申请号 US19990429022 申请日期 1999.10.29
申请人 NIPPONDENSO CO., LTD. 发明人 HAYAKAWA HIROSHI;FUKUMOTO HARUTSUGU;TANAKA HIROAKI
分类号 G06F9/32;G06F9/38;(IPC1-7):G06F9/42 主分类号 G06F9/32
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