TIMING-EXTRACTION CIRCUIT

摘要

PROBLEM TO BE SOLVED: To extract a clock signal, corresponding to the signal of a desired bit rate from a plurality of signals of bit rates. SOLUTION: At the time of receiving the signal of frame constitution including the signals of the different bit rates in respective sections divided, by a prescribed time interval by a division signal, a filter circuit 12 takes out the frequency signal of the division signal. The frequency of the division signal is multiplied in a multiplication circuit 18 to the frequency of the desired bit rate and is inputted to PLL circuits (13, 14 and 15) as a reference signal. The clock signal corresponding to the signal of the desired bit rate is extracted.