发明名称 INTEGRATED DRAM MEMORY CELL AND DRAM MEMORY
摘要 PROBLEM TO BE SOLVED: To decrease an area of a DRAM memory cell. SOLUTION: A memory cell 51 has at least a memory capacitor 52 and a selection transistor 12 which are intrinsically formed in a region of a rectangular cell region 59. The rectangular cell region 59 has a larger range in a longitudinal direction L than in a widthwise direction B. It is wired to a periphery of a cell via word lines 56, 57 and a bit line 55, or can be wired thereto. The word lines 56, 57 and the bit line 55 are transmitted onto the memory cell 51 and are directed at least intrinsically perpendicular to each other.
申请公布号 JP2001291848(A) 申请公布日期 2001.10.19
申请号 JP20010068253 申请日期 2001.03.12
申请人 INFINEON TECHNOLOGIES AG 发明人 FREY ALEXANDER;WEBER WERNER;SCHLOSSER TILL
分类号 H01L27/108;G11C11/407;G11C11/4097;H01L21/8242;H01L27/02 主分类号 H01L27/108
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