发明名称 ADDRESS OUTPUT CIRCUIT
摘要 PROBLEM TO BE SOLVED: To shorten an access time when a memory is accessed by an address output circuit. SOLUTION: This circuit has not such constitution that an address signal given by a host device is latched and this latched contents are decoded, but has such constitution that an address signal is decoded directly before latching and a decoded result is latched. That is, a given address signal is decoded directly by a decoding circuit D, and a memory cell is activated in accordance with this decoded result. This decoded result is latched in a latch circuit K with timing with which a chip selecting signal is shifted to a valid state, and the memory cell is activated by address signals AD0-AD3 being this latched contents.
申请公布号 JP2001291391(A) 申请公布日期 2001.10.19
申请号 JP20000103841 申请日期 2000.04.05
申请人 SEIKO EPSON CORP 发明人 TOKUDA YASUNOBU
分类号 G11C11/413;G11C11/408;(IPC1-7):G11C11/413 主分类号 G11C11/413
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