发明名称 PREFETCH FOR TLB CACHE
摘要 PROBLEM TO BE SOLVED: To provide a memory management unit in order to support a protection mechanism and dynamic memory management in a multiprocessor environment. SOLUTION: The memory management unit (42) used by a digital signal processor (30) or another processor is provided with a circuit for responding to a prefetch command and performing conversion from a virtual address into a physical address. The prefetch command is started by conducting a write access to a dummy register. When the prefetch command is detected, a TLB is checked in order to confirm whether or not a physical base address related to a generated virtual address currently exists in the TLB. When the physical base address does not exist, a walking table logic performs the table look-up of a main memory (34) in order to acquire conversion results. The logic operation of the walking table logic is performed without interrupting a continuous operation by a DSP core (36).
申请公布号 JP2001290706(A) 申请公布日期 2001.10.19
申请号 JP20010100260 申请日期 2001.03.30
申请人 TEXAS INSTR INC <TI> 发明人 CHAUVEL GERARD;LASSERE SERGE;D INVERNO DOMINIQUE BENOIT JACQUES;EDWARD FERGUSON
分类号 G06F9/312;G06F9/38;G06F12/08;G06F12/10;(IPC1-7):G06F12/10 主分类号 G06F9/312
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