发明名称 DELAY CALCULATING METHOD FOR HIERARCHICAL DESIGN
摘要 PROBLEM TO BE SOLVED: To calculate a correct delay value at a layer border. SOLUTION: Whole chains T$04 to T$13 are divided to generate 1st partial chains T$04 to T$10 and 2nd partial chains T$01 to T$03 and T$11 to T$13 and the 1st delay quantity TD (4-10) of the 1st partial chains is calculated. Then 3rd partial chains T$01 to T$05 and T$09 to T$13 consisting of associative elements in end areas of the 1st partial chains and the 2nd partial chains are generated and the 2nd delay quantities TD (1-5) and TD (9-13) of the 3rd partial chains are calculated; and the associative elements T$05 and T$09 at the end parts of the associative elements T$04 to T$05 and T$09 to T$10 are disconnected from the 3rd partial chains and their 3rd delay quantities D5 and D9 are calculated. The 3rd delay quantities D5 and D9 are subtracted from the 2nd delay quantities to calculate 4th delay quantities TD (1-4) and TD (10-13), which are overwritten to the 1st delay quantity by the associative elements to calculate the delay quantity of the whole chain. Inaccurate values are erased and the correct delay relation between the whole chain and partial chains is established.
申请公布号 JP2001290855(A) 申请公布日期 2001.10.19
申请号 JP20000108604 申请日期 2000.04.10
申请人 NEC CORP 发明人 SAITO WATARU
分类号 G06F17/50;H01L21/82;(IPC1-7):G06F17/50 主分类号 G06F17/50
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