发明名称 SIGNAL PROCESSOR
摘要 <p>PROBLEM TO BE SOLVED: To reduce the circuit scale of a discrete cosine transformation(DCT) device. SOLUTION: One column or one row required in one-dimensional DCT in the direction of the row or column, which is performed in the second time, is transformed by one-dimensional DCT performed in the direction of the row or column with respect to M×N-pieces of data f(x, y), N-pieces in the row direction and N-pieces in the column direction. In one-dimensinoal DCT performed in the second time, one-dimensional DCT is performed from data of one column or one row, N-pieces of transformation coefficients in one column or M-pieces in one row are outputted, and the accumulation of data between one-dimensional DCT for the first time and the second time is set to be the data buffer of N-pieces in one column×k bits or M-pieces in one row×k-bits.</p>
申请公布号 JP2001290797(A) 申请公布日期 2001.10.19
申请号 JP20000106697 申请日期 2000.04.04
申请人 HITACHI LTD 发明人 KOBAYASHI YUKIFUMI;HATAE HIROSHI;WATANABE HIROMI
分类号 G06F17/14;H03M7/30;H04N19/42;H04N19/423;H04N19/60;H04N19/625;(IPC1-7):G06F17/14 主分类号 G06F17/14
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